`timescale 1ms/1ms
module test_condroller ();
reg  CLK,RESET,S;
wire  HG,HY,HR,FG,FY,FR;
//output [2:0] Hstate,Fstate;
wire [3:0] TimerH,TimerL;




// 实例化被测试模块
  controller test (
    .CLK(CLK),
    .RESET(RESET),
    .S(S),
    .HG(HG),
    .HY(HY),
    .HR(HR),
    .FG(FG),
    .FY(FY),
    .FR(FR),
    .TimerH(TimerH),
    .TimerL(TimerL)
  );   
initial 
  begin
    RESET=1'b0;
    CLK=1'b0;
     #100 RESET = 1'b1;
    S=1'b0;

    //#20  S=1'b0;
  end

always #5
    begin
       CLK = ~CLK;
      // Hstate={HG,HY,HR};
     //  Fstate={FG,FY,FR};
    end
always #10
    begin
       #20  S={$random}%2;
      // Hstate={HG,HY,HR};
     //  Fstate={FG,FY,FR};
    end
  
   
endmodule